In a 2010 article titled "SRTP AES Optimization" I presented a method to make SRTP AES run significantly quicker. Unfortunately, there were some caveats: Packet length had to be 4096 bytes or less and a multiple of 16, and the target CPU was expected to be big endian. Let's try to address these issues in a new and improved version that will run on any 32-bit CPU.
The NVidia Tegra X1 has a Maxwell-based GPU with a theoretical FP32 peak of 512 GFLOPS per second. It can easily be programmed using OpenGL GLSL shaders. However, making fast GPU code is different from making fast CPU code. 3 non-typical GPU jobs are implemented in fragment shaders and optimized for better performance. Videos and source code is included.
Drop-in replacement for aes_core.c that's significantly faster. Includes a second look at how to do the last round in less than half the instructions.
A look at how to do bilinear picture scaling on the Tilera TILE-Gx. Two different approaches are tried out. Measurements are done on different core counts and data sizes. Uses a new parallelization library, presented in the article, to split the work across multiple cores.
Raytracing is a job well suited for multicore CPUs. Challenge of the day: Make a raytracer for the Tilera TILE-Gx36 that's quick enough to output 1920x1080p60 video. Source code, pictures, videos and performance measurements included.
A RGB to YUV conversion routine for Tilera TILE-Gx that uses the new dual dot product instructions for maximum efficiency.
Optimizing for the Tilera TILE-Gx CPU is very different from Intel SSE2. An attempt to get optimal performance using 8 bit multipliers as much as possible.
A common error in this class of conversion routines on SSE2 is too conservative use of multipliers, leading to complicated data shuffling before and/or after the multiplications. SSE2 multipliers are inherently cheap to use, so let's try to maximize their usage instead.
A look at the SSE2 3x3 box filter used as example code in the Halide language specification. I get significantly better results using normal C code and SSE2 intrinsics. The code is also comprehensible.
A TILE-Gx core can issue 3 instructions in parallel, given a set of strict restrictions. This paper explores how to exploit that in an AES encryption routine using TILE-Gx intrinsics.
Calculating SHA1 hashes on SRTP packets can be quite costly on low end CPUs. Since lengths etc. are static, let's try to strip out the code that actually does SHA1 calculation in OpenSSL and make it as fast as possible. Tests are performed on a Freescale MPC8270 CPU.
A "feature" in the SRTP specification makes it possible to reduce the CPU cost of AES encryption and decryption by 30%.