The Xmas Demo 2023 for the NVidia Jetson AGX Orin Developer Kit. How would the TX2-based 2017 and 2020 Xmas Demos look on 8 times more powerful hardware? We retweaked all the old shaders, replaced some crap ones, and tied it all together in a 4 minutes long hiqh quality video. Full source code included.
Presenting Edgehog: A method for doing fractal rectangle checking quickly on multiple ARM Neon cores. The output is rendered by a GPU using the Depth First Algorithm (DFA) described in the article "GPU Hacks" (Corneliusen 2016, 2017). This makes it possible to render 1080p60 depth 256 fractals on a dainty NVidia Jetson Nano. Full source code included.
Introducing a fast Lanczos-2 image scaler for ARM Neon written in C and intrinsics. It uses a unique method for applying separable filters described in the article "Exploiting the Cache: Faster Separable Filters" (Corneliusen 2018). An ARMv7 Neon Assembler implementation from 2014 gets a makeover. Full source code included.
(PDF, 368KB) It's been two years since the launch of the discordant book Real Programming. This 10-page article sums up all the main themes and looks at what has happened since then.
The Xmas Demo 2022 for the NVidia Jetson AGX Orin Developer Kit. Shader code available for download. A more polished version of last year's demo that exploits the extra power in the Orin.
The Xmas Demo 2021 for the NVidia Jetson AGX Xavier. Full source code available. It demonstrates Sjur's new 3D engine called V73D and has animated objects using inverse kinematics. And a bunch of recycled and optimized shaders and stuff, and some music too.
A book about programming, programmers, programs, and pop culture. Co-authored with Sjur Julin. Tired of crap books promising to teach you the latest programming fad in 21 days? This one is the polar opposite! It contains a lot of real code written in real programming languages like C and assembler. A recurring theme is criticism of modern development methods, software management, languages, and compilers.
The Xmas Demo 2020 is an updated version of the one from 2017. The source code from 2017 was revised to run on any graphics card and CPU. It still runs on the target NVidia Tegra X2 in 60 fps. Full source code available. Music and graphics by Sjur.
A 2019 remastering of the Triumph Amiga demos Dreamscape and Eclipse, released at The Gathering 1996 and 1997. We recovered the original video and music files from my Amiga, including some unused hi-res images. The music was remixed, the font was replaced, the video files were resampled, scaled to 1080p and denoised and retimed to the new music. It's low res, it's gritty, it's 1996 all over again, with a 2019 flair.
Introduces a unique and extremely fast method for applying separable filters. A Lanczos-2 picture scaler is used as example. SSE2 intrinsics and ARM Neon Assembler solutions are provided.
Several dubious GLSL optimization techniques were used to make this demo run in 60 fps on the TX2 256-core GPU. If you're looking for precise math, look elsewhere. Close enough will have to do on that GPU! Everything should fly by in 60 fps. Full source code available.
A second attempt at raytracing on the Tilera TILE-Gx. The TILE-Gx has very limited floating-point support in hardware, so let's try using fixed point math instead. Unfortunately, calculating square roots is very time consuming. An alternative approach is explored where custom conversion routines and integer math does this quickly enough to render 40 spheres in 1080p60. Videos and source code included.
The GPU only raytracer described in my 2016 article "GPU Hacks" can trace 80 spheres at 60 fps on the NVidia Tegra X1. This new article describes how to use CPU preprocessing to boost the sphere count to 128 with minimal changes to the GPU part. Videos and source code is included.
In a 2010 article titled "SRTP AES Optimization" I presented a method to make SRTP AES run significantly quicker. Unfortunately, there were some caveats: Packet length had to be 4096 bytes or less and a multiple of 16, and the target CPU was expected to be big endian. Let's try to address these issues in a new and improved version that will run on any 32-bit CPU.
The NVidia Tegra X1 has a Maxwell-based GPU with a theoretical FP32 peak of 512 GFLOPS per second. It can easily be programmed using OpenGL GLSL shaders. However, making fast GPU code is different from making fast CPU code. 3 non-typical GPU jobs are implemented in fragment shaders and optimized for better performance. Videos and source code is included.
Drop-in replacement for aes_core.c that's significantly faster. Includes a second look at how to do the last round in less than half the instructions.
A look at how to do bilinear picture scaling on the Tilera TILE-Gx. Two different approaches are tried out. Measurements are done on different core counts and data sizes. Uses a new parallelization library, presented in the article, to split the work across multiple cores.
Raytracing is a job well suited for multicore CPUs. Challenge of the day: Make a raytracer for the Tilera TILE-Gx36 that's quick enough to output 1920x1080p60 video. Source code, pictures, videos, and performance measurements included.
Port of Quake for the TILE-Gx mega-multicore CPU. Number of Quakes possible to run in parallel is only limited by your screen size. Custom TILE-Gx specific scalers, including 2x and 3x EPX.
A RGB to YUV conversion routine for Tilera TILE-Gx that uses the new dual dot product instructions for maximum efficiency.
Optimizing for the Tilera TILE-Gx CPU is very different from Intel SSE2. An attempt to get optimal performance using 8-bit multipliers as much as possible.
A common error in this class of conversion routines on SSE2 is too conservative use of multipliers, leading to complicated data shuffling before and/or after the multiplications. SSE2 multipliers are inherently cheap to use, so let's try to maximize their usage instead.
A look at the SSE2 3x3 box filter used as example code in the Halide language specification. I get significantly better results using normal C code and SSE2 intrinsics. The code is also comprehensible.
A TILE-Gx core can issue 3 instructions in parallel, given a set of strict restrictions. This paper explores how to exploit that in an AES encryption routine using TILE-Gx intrinsics.
Calculating SHA1 hashes on SRTP packets can be quite costly on low end CPUs. Since lengths etc. are static, let's try to strip out the code that actually does SHA1 calculation in OpenSSL and make it as fast as possible. Tests are performed on a Freescale MPC8270 CPU.
A "feature" in the SRTP specification makes it possible to reduce the CPU cost of AES encryption and decryption by 30%.
A look at the hidden menu in TANDBERG MXP video conferencing units, some obscure prototypes, and some more well-known prototypes.
Port of Doom for the TILE-Gx mega-multicore CPU. Number of Dooms possible to run in parallel is only limited by your screen size. Custom TILE-Gx specific scalers, including 2x and 3x EPX.
Code that might be interesting for code archaeologists and full schematics for HomePilot 2.0. Some random pictures from back then added in 2023. Was the 2.0 version ever released? Signs point to no.
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under the hood
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